1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which may minimize damages of semiconductor devices due to ion implantation processes by naturally implementing a lightly doped drain (LDD) structure with a minimum processes.
2. Description of the Prior Art
Recently, as the size of semiconductor devices and the channel length of transistors are rapidly reduced, various kinds of defects including a punch-through are also greatly increased in its incidence, in proportion to such reduction of the channel length.
In previous consideration of the defects such as punch-through, the prior art has proposed a method of manufacturing a semiconductor device, wherein an LDD structure is formed to secure a shallow junction between a source electrode and a drain electrode of transistor, and by such LDD structure, an electric field strength between the source and drain electrodes are naturally reduced.
An LDD structure of the prior art is disclosed in U.S. Pat. No. 6,124,610 entitled “Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant”, U.S. Pat. No. 6,107,129 entitled “Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance”, Japanese Patent Application Publication No. 1998-12870 entitled “Semiconductor devices and manufacturing method thereof”, EP399,664 entitled “Forming and removing polysilicon LDD spacers” and EP595,484 entitled “NMOS LDD PMOS HALO IC process for CMOS transistors”.
First, as shown in FIG. 1, in the prior art, a substrate 10 is provided whose active region is defined by an isolating layer 10a. A gate electrode 13 having a gate oxide layer pattern 11 and a gate poly layer pattern 12 on the active region of the substrate 10 is formed.
Then, as shown in FIG. 2, by performing an ion implantation process using the gate electrode 13 as an ion-implantation mask, impurities are lightly doped onto the substrate 10, forming a source/drain electrode 15 with low concentration for LDD structure on the substrate 10 adjacent to the gate electrode 13.
Then, as shown in FIG. 3, spacers 16 are formed on both sidewalls of the gate electrode 13.
Then, as shown in FIG. 4, by performing an ion implantation using the spacers 16 as an ion implantation mask, impurities with high concentration are implanted into the substrate 10, forming a source/drain electrode 17 with high concentration onto both sides of the gate electrode 13.
Finally, certain subsequent process, such as annealing process, is performed, thus forming a semiconductor device with LDD structure.
In such prior system as described above, in order to form the LDD structure source/drain electrode 15 with low concentration, a process of implanting impurities into the substrate 10 should be preceded, so that certain impact shocks due to implantation of impurities might be applied to the surface of substrate 10, with the result that a lattice structure of partial silicon atoms constituting the surface of substrate 10 being considerably destroyed.
In this case, when certain subsequent process, for example, an annealing process, is forcedly performed without conducting separate measures, partial silicon atoms with their lattice structure destroyed due to impact shocks of impurities become separated from the surface of substrate 10 and then being scattered outside by heat applied during the annealing process, thus generating unnecessary defects such as voids on the surface of substrate 10.
Such voids continuously have a bad influence on a certain construction formed on the substrate 10, so that product quality of finally finished semiconductor devices may be degraded below a certain level unless separate measures are conducted.
Meanwhile, in the prior system, as mentioned above, the source/drain electrode 15 for LDD structure with low concentration is formed by using the gate electrode 13 as an ion implantation mask, so that the gate electrode 13 may have a limit in a size reduction.
The reason of which is because, when the size of the gate electrode 13 has been considerably reduced, a distance between the lightly doped source/drain electrode 15, which is formed dependently by using the gate electrode 13 as an ion implantation mask, becomes so narrower, with the result that the generation of bad phenomenon such as a punch-through being caused.
As a result, in the prior art, nevertheless of current situation in that the size of semiconductor devices being reduced, the size thereof is hardly reduced to the optimum, so that it is difficult to increase a performance of semiconductor devices.